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? 2 ? × 255 = 2.55 sec
?
Data Sheet
The ADE7816 contains four zero-crossing detection circuits,
one dedicated for the voltage channel and three for the current
channels. A group of current channels (A, B, C or D, E, F) must
be selected by Bit 14 (CHANNEL_SEL) of the COMPMODE
Group section). When switching between channel groups, a set-
tling time of 10 ms (50 Hz) or 8 ms (60 Hz) is required. Each
circuit drives one flag in the STATUS1 register (Address 0xE503).
For example, if a zero crossing occurs on the voltage channel,
Bit 9 (ZXV) in the STATUS1 register goes high. If a zero-crossing
event occurs on Current Channel A and the CHANNEL_SEL
bit in the COMPMODE register is set to 0, Bit 12 (ZXI1) in the
STATUS1 register is set to 1.
Zero-Crossing Timeout
Each zero-crossing detection circuit has an associated timeout
register. This register is loaded with the value that is written into
the 16-bit ZXTOUT register (Address 0xE60D) and is decremented
by 1 LSB every 62.5 μs (16 kHz clock). The register is reset to the
ZXTOUT value every time a zero crossing is detected. The default
value of this register is 0xFFFF. If the timeout register decrements
to 0 before a zero crossing is detected, the corresponding STATUS1
bit is set.
There is a zero-crossing timeout circuit that is dedicated to the
voltage channel. For example, if a zero-crossing timeout event
ADE7816
Bits[4:2] (PEAKSELx) of the MMODE register (Address 0xE700)
can be set to 0 to disable a channel. Note that one PEAKSELx
bit must always be set to 1 to enable the feature.
The results of the current and voltage peak detection are stored
in the lowest 24 bits of two 32-bit, unsigned registers, IPEAK
(Address 0xE500) and VPEAK (Address 0xE501). The peak
detection measurements are updated at the end of the peak cycle
specified in the PEAKCYC register. At that time, Bit 24 (PKV)
and Bit 23 (PKI) in the STATUS1 register go high, signaling
a peak event. To determine which current channel caused the peak
event, Bits[26:24] (IPCHANNELx) in the IPEAK register must
be read.
Setting the PEAKCYC Register
The 8-bit, unsigned PEAKCYC register contains the program-
mable peak detection period. The peak detection period is the
number of half line cycles over which the peak measurement is
measured. Each LSB of the PEAKCYC register corresponds to one
half line cycle period. The PEAKCYC register holds a maximum
value of 255.
At 50 Hz, the maximum peak cycle time is 2.55 seconds.
? 1 ?
? 50 ?
At 60 Hz, the maximum peak cycle time is 2.125 seconds.
?
? 2 ? × 255 = 2.125 sec
occurs on the voltage channel, Bit 3 (ZXTOV) in the STATUS1
register is set. There are three zero-crossing timeout circuits for
? 1
? 60
?
?
the six current channels. A group of current channels, A, B, C or D,
E, F, must be selected by the CHANNEL_SEL bit of the
Group section). For example, if a zero-crossing timeout event
occurs on Current Channel D and the CHANNEL_SEL bit in
the COMPMODE register is set to 1, Bit 6 (ZXTOI1) in the
STATUS1 register is set to 1.
The resolution of the ZXTOUT register is 62.5 μs (16 kHz clock)
per LSB. Therefore, the maximum timeout period for an interrupt
is 4.096 sec (2 16 /16 kHz).
PEAK DETECTION
OVERCURRENT AND OVERVOLTAGE DETECTION
The ADE7816 provides an overcurrent and overvoltage feature
that detects whether the absolute value of the current or voltage
waveform exceeds a programmable threshold. This feature uses
the instantaneous voltage and current signals. The two registers
used to set the voltage and current channel threshold are OVLVL
(Address 0xE508) and OILVL (Address 0xE507), respectively.
The OILVL threshold register determines the threshold for all
current channels. The default value of the OVLVL and OILVL
registers is 0xFFFFFF, which effectively disables the feature.
The ADE7816 includes an instantaneous peak detection feature
that stores the maximum absolute value reached on the current
and voltage channels over a fixed number of half line cycles.
The PEAKCYC register (Address 0xE703) stores the number of
half line cycles used for all peak measurements.
The peak detection feature is available on the voltage channel
and three of the current channels. A group of current channels
(A, B, C or D, E, F) must be selected by the CHANNEL_SEL bit of
VOLTAGE CHANNEL
OVLVL
OVERVOLTAGE
DETECTED
Group section). When switching between current channel groups,
no additional settling time is required. However, the PEAKCYC
register should be rewritten to reset the measurement. By default,
all three current channels are included in the peak detection
measurement. If only one or two current channels are required,
BIT 18 (OV) OF
STATUS1
STATUS1[18]
CANCELLED BY A
WRITE OF STATUS1
WITH OV BIT SET.
Figure 34. Overvoltage Detection
Rev. A | Page 27 of 48
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